Conventional HEMT (high electron mobility transistor) devices fabricated in GaN technology are based on etching a gate opening into the first level surface passivation eventually including a gate base recess into the barrier layer (e.g. AlGaN), followed by deposition of an optional gate dielectric and a gate electrode. The electrode is then patterned in a second step independently from the gate base opening. This leads to an overlap of the gate electrode beyond the gate base defined by the process and lithography overlay tolerances. That is, the conventional GaN HEMT gate has a T-shape. This overlap of the gate toward the drain direction leads to an unwanted large gate-to-drain capacitance Cgd.
The gate-to-drain capacitance Cgd problem can be circumvented by skipping the first level surface passivation and patterning the gate electrode directly on the barrier layer (e.g. AlGaN with GaN cap) of the GaN HEMT. However, this approach causes degradation of the barrier surface condition when the gate pattering is done by plasma etching which is needed to realize short gate lengths e.g. <1 μm. This approach also does not allow the usage of a so-called in-situ passivation scheme where the barrier layer is capped with a SiN layer already available in the epitaxy tool. Deposition of this passivation layer after the gate electrode is formed limits the available process options, as e.g. an LPCVD (low-pressure chemical vapor deposition) nitride is not possible after the gate metal electrode is formed.